Many memory devices utilize memory built-in self-test (BIST) techniques whereby some or all of the memory storage locations are analyzed by embedded circuitry to identify faulty memory storage locations. Repair information regarding the faulty memory storage locations (e.g. the addresses of the faulty memory storage locations) is stored in a set of latches dedicated to the storage of test information only. The repair information then can be retrieved from these dedicated latches for the purpose of repairing the faulty memory storage locations, such as by rerouting the corresponding address to a back-up memory storage location. However, as the storage capacity of memory devices increases, so does the number of dedicated latches needed to store the test information. This increase in the number of latches dedicated to storing memory test information has resulted in a corresponding increase in the size, complexity, and cost of conventional memory devices.
In an effort to reduce the number of dedicated latches, some memory devices divide their memory arrays into separate regions for testing and run multiple passes of the test process. After each pass, the repair information for the tested region is shifted out for the next test pass, thereby reducing the size of the repair information for each pass, and thus the number of dedicated latches needed to store the repair information. However, this technique is complex and inefficient due to the repetition of the test process. As an alternate technique, some memory devices utilize a compression engine to compress the test information to fit into a smaller number of dedicated latches. However, like other conventional solutions, the implementation of the compression engine increases the complexity of the memory device and reduces the performance of the test process. Accordingly, an improved technique for storing test information for memory test and repair purposes would be advantageous.